The present invention relates to the fabrication of semiconductor integrated circuits (IC's) and flat panel displays. More particularly, the present invention relates to improved methods and apparatus for etching through the silicon dioxide-containing layer of a substrate during semiconductor device fabrication.
In the fabrication of semiconductor devices, different layers may be deposited, patterned, and etched to form the desired structures on the substrate (i.e., a glass panel or a semiconductor wafer). In some semiconductor devices, titanium nitride (TiN) is often employed as an etch stop layer during the etching of an overlying silicon dioxide-containing layer or as an antireflective coating (ARC) layer. By way of example, when the TiN layer is employed under a silicon dioxide-containing layer, such as a PETEOS (plasma enhanced tetraethylorthosilicate), BSG (boron-doped silicate glass), USG (undoped silicate glass), BPSG (borophosphosilicate glass), or the like, the TiN material may serve as an etch stop during a via etch through the silicon dioxide-containing layer. Thereafter, the TiN material may serve as a barrier or glue material between the subsequently deposited tungsten or aluminum plugs and any underlying metal layer (e.g., copper or aluminum).
To facilitate discussion, FIG. 1 illustrates a cross section view of some exemplary layers of a substrate. With reference to the figures herein, it should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers. In FIG. 1, there is shown an underlying layer 102, representing any layer or layers that may underlie a TiN layer on a substrate. For example, underlying layer 102 may represent the substrate itself or may represent layers subsequently deposited and etched prior to the deposition of a TiN layer 104. TiN layer 104 is shown disposed between underlying layer 102 and a subsequently deposited silicon dioxide-containing layer 106. Although the layers of FIG. 1 have not been shown to scale to facilitate ease of illustration, TiN layer 104 is typically much thinner than silicon dioxide-containing layer 106.
In some cases, it is often desirable to etch through silicon dioxide-containing layer 106 down to the interface between silicon dioxide-containing layer 106 and TiN layer 104 without etching completely through TiN layer 104. In these cases, TiN layer 104 may function as the etch stop layer, i.e., it is desirable that the etching stops before TiN layer 104 is etched through. As semiconductor devices density increases over time, however, it becomes increasingly difficult to etch, using prior art etch techniques, through silicon dioxide-containing layer 106 without damaging underlying TiN layer 104. This is because the TiN layer is typically quite thin in modern high density semiconductor devices since a thinner TiN layer is more conducive to the manufacture of high density devices.
In the prior art, the etching of the oxide layer (i.e., the silicon dioxide-containing layer) was typically accomplished using a C.sub.X F.sub.Y chemistry (e.g., CF.sub.4, C.sub.2 F.sub.6, C.sub.3 F.sub.8, or the like ). The C.sub.X F.sub.Y chemistry was selected primarily for its high etch rate through the oxide layer. By way of example, the prior art C.sub.X F.sub.Y chemistry typically etches through the oxide layer at a rate of greater than about 2,000 angstrom per minute. Unfortunately, the C.sub.X F.sub.Y chemistry has a relatively low selectivity toward TiN. That is, the prior art C.sub.X F.sub.Y chemistry also etches the TiN material at a relatively significant etch rate. For example, the C.sub.X F.sub.Y chemistry typically has an oxide-to-TiN selectivity in the range of 7 to 1 to 10 to 1 (i.e., the C.sub.X F.sub.Y etches through the oxide material 7 to 10 times as fast as it etches through the TiN material).
In FIG. 2, a trench 108 is etched through silicon dioxide-containing layer 106. TiN layer 104 is intended as the etch stop layer and should have stopped the oxide etch before the oxide etch proceeds through to underlying layer 102. Nevertheless, the low TiN selectivity of the prior art chemistry causes TiN layer 104 of FIG. 2, which is quite thin to enable the semiconductor devices to pack closely together, to be completely etched through under trench 108. When the TiN layer is inadvertently etched through, the bottom of trench 108 may present an irregular topology to subsequent processes, which may cause the fabricated devices to fail due to, for example, unintended misalignment of layers. Further, the absence of the TiN barrier material at the bottom of the trench may cause ion leakage and/or other unintended electrical characteristics in the fabricated devices. In a typical situation, TiN layer 104 may be etched through either during the main oxide etch step or during the oxide over-etch step.
The low oxide-to-TiN selectivity of the prior art C.sub.X F.sub.Y chemistry also poses significant problems during the etching of multi-level oxide layers. To facilitate discussion, FIG. 3 depicts a multi-level oxide structure 300, including a multi level oxide layer 302. For illustration purposes, multi-level oxide layer 302 includes a thick region 304 and a thin region 306 although other regions of various thicknesses may also be present within multi-level oxide layer 302. Multi-level oxide layer 302 is disposed on TiN layer 104, which is intended to function as an etch stop during the etching of multi-level oxide layer 302. For consistency, underlying layer 102 is also shown disposed below TiN layer 104.
In some cases, it may be desirable to simultaneously create vias in thick region 304 and thin region 306 of multi-level oxide layer 302. Since thin region 306 is thinner than thick region 304, via etching in thin region 306 may be completed before the oxide material in thick region 304 is completely etched through. If the oxide etch is allowed to continue to facilitate etching of the via in thick region 304, the low oxide-to-TiN selectivity of the prior art C.sub.X F.sub.Y chemistry may undesirably etch through the TiN material within the via in thin region 306.
On the other hand, if the oxide etch step is shortened to prevent damage to the TiN material underneath the via in thin region 306, the via through thick region 304 of multi-level oxide layer 302 may not be completely etched through. As is apparent, the low oxide-to-TiN selectivity of the prior art chemistry poses serious problems while etching multi-level oxide layers of modern high density ICs.
In view of the foregoing, there are desired improved techniques for etching through the oxide layer during the manufacture of semiconductor devices. The improved techniques preferably provide a high oxide-to-TiN selectivity to substantially reduce damage to the underlying TiN layer during oxide etching.